各位好
我們有一個題目是寫
Please design a circuit to detect the sequence 1101. A sequence detector
produces out = 1 if the consecutive input signals are 1101; otherwise, out =
0.For example,
example 1
-----------|.....|-------|.....|-------
in : 0,0,0,1,1,0,1,1,0,0,1,1,0,1,0,0...
out: 0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,0...
.................^.............^.........
example 2
-----|.....|.....|-------------
in : 1,1,0,1,1,0,1,0,0,0,1,0,0...
out: 0,0,0,1,0,0,1,0,0,0,0,0,0...
...........^.....^...............
助教給的wave圖長這樣
https://imgur.com/gallery/HqGtA5M我想問的是下面這張圖，有符合上面這個題目的敘述嗎?
https://imgur.com/gallery/iGcWcjV因為設計成正緣觸發，兩張圖的差異就變成了在最後一個1時
一個是0 -> 1，另一個是1 -> 0
讓我搞不太清楚應該是怎麼做
剛學verilog
如果問題很模糊的話，我會再解釋更清楚一點的，謝謝:)
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